Feed-forward equalizer architectures

ABSTRACT

Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. patent application Ser. No.13/763,312, filed on Feb. 8, 2013, which claims priority to U.S.Provisional Patent Application Ser. No. 61/597,491, filed on Feb. 10,2012, the disclosures of which are incorporated herein by reference.

TECHNICAL FIELD

The field relates generally to equalization architectures and, inparticular, circuits and methods for efficient implementation offeed-forward equalization architectures employing sample-and-holdcircuitry.

BACKGROUND

A feed-forward equalization (FFE) circuit is a transversal filter thatmay be employed in multi-gigabit/s serial link transceivers tocompensate for the frequency dependent loss of communication channels.Since these channels typically have a low-pass transfer function, an FFEis programmed to have high-pass characteristics to effectivelycompensate for the channel transfer function and reduce the intersymbolinterference introduced by the channel. In principle, the FFE can beimplemented in either the transmitter or the receiver.

Traditionally, FFE realization in the transmitter has been preferred dueto its ease of implementation and lower power and area costs. However,placing the FFE in the transmitter has important disadvantages. Sincethe quality of the received signal is only known in the receiver,automatic adaptation of the FFE coefficients for optimum linkperformance requires a back channel from receiver to transmitter,something which is often unavailable (especially when the transmitterand receiver are sourced from different vendors). Since the peak voltageswing of the transmitter is limited by available supply voltages,transmit-side FFE compensates for high-frequency loss in the channel notby increasing the amplitudes of high-frequency signals but by decreasingthe amplitudes of low-frequency signals. This results in a smallerreceived signal, which is more vulnerable to noise sources such ascrosstalk.

One way to avoid the disadvantages of transmit-side FFE is to implementthe equalizer in the receiver. To avoid the difficulties of implementingan actual receive-side FFE, peaking amplifiers are commonly employed inserial link receivers. However, peaking amplifiers do not provide enoughflexibility in the placement of their poles and zeroes, making itdifficult to accurately match the equalizer to the channelcharacteristics. Moreover, peaking amplifiers are not compatible withwell-known equalizer adaptation algorithms (e.g. Least Mean Squares orLMS). Thus, there is a strong motivation to develop circuit techniquesthat overcome the practical difficulties of implementing receive-sideFFE systems.

SUMMARY

Embodiments of the invention generally include equalizationarchitectures and, in particular, circuits and methods for efficientimplementation of feed-forward equalization architectures employingsample-and-hold circuitry.

In one embodiment of the invention, a feed-forward equalization circuitincludes delay circuitry and a current-integrating summer circuit. Thedelay circuitry includes n parallel sample-and-hold circuits that areclocked by multiphase clocks to generate n time-delayed versions of aninput data signal. The current-integrating summer circuit includes afirst power supply node, an output node and a first switch connectedbetween the first power supply node and the output node. The firstswitch is responsive to a reset control signal to connect the outputnode to the first power supply node and precharge a capacitance of theoutput node during a reset period of the current-integrating summercircuit, and to disconnect the output node from the first power supplynode during an integrating period of the current-integrating summercircuit. The current integrating summer circuit further includes intransconductance amplifier circuits connected to the output node. Eachof the m transconductance amplifier circuits receives as input a datasignal that corresponds to one of the n time-delayed versions of theinput data signal, and generates an output current on the output node.The output currents from the in transconductance amplifier circuitscollectively charge or discharge the capacitance of the output nodeduring the integration period. Further, at least one transconductanceamplifier circuit of the m transconductance amplifier circuits includesa gating control circuit, wherein the gating control circuit isresponsive to a gating control signal to disable the at least onetransconductance amplifier circuit during a portion of the integrationperiod in which the data signal input to the at least onetransconductance amplifier circuit is invalid.

In another embodiment, a method is provided for equalizing a datasignal. The method includes generating n time-delayed versions of aninput data signal and inputting m data signals to m feed-forwardequalization (FFE) taps of a current-integrating summer circuit. Each ofthe m data signals corresponds to one of the n time-delayed versions ofthe input data signal. A capacitance is precharged to a precharge levelduring a reset period of the current-integrating summer circuit. Anoutput current is generated by each of the m FFE taps during anintegration period of the current-integrating summer circuit, whereinthe output currents from the m FFE taps collectively charge or dischargethe capacitance during the integration period. A gating control signalis applied to at least one FFE tap of the m FFE taps during theintegration period of the current-integrating summer circuit to disablethe at least one FFE tap during a portion of the integration period inwhich the data signal input to the at least one FFE tap is invalid.

These and other embodiments of the invention will become apparent fromthe following detailed description of exemplary embodiments thereof,which is to be read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a feed-forward equalizer circuit.

FIG. 2A is a block diagram of a feed-forward equalizer circuitcomprising delay circuitry that is implemented using a plurality ofsample-and-hold circuits to generate time-shifted data signals.

FIG. 2B shows example waveforms that illustrate an operating mode of thefeed-forward equalizer circuit shown in FIG. 2A.

FIG. 3 is a block diagram of an n-tap current-integrating summer circuitfor a feed-forward equalizer circuit, according to an embodiment of theinvention.

FIG. 4A is a schematic circuit diagram of a current-integratingamplifier circuit according to an embodiment of the invention, which canbe used to implement the n-tap current-integrating summer circuit shownin FIG. 3.

FIG. 4B shows example waveforms that illustrate an operating mode of thecurrent-integrating amplifier circuit of FIG. 4A, according to anembodiment of the invention.

FIG. 5 is a schematic circuit diagram of a 4-tap current-integratingsummer circuit for a feed-forward equalizer circuit, which is based onthe circuit structures of FIGS. 3 and 4A, according to an embodiment ofthe invention.

FIG. 6 shows example waveforms that illustrate an operating mode of aquarter-rate feed-forward equalizer circuit that employs the 4-tapcurrent-integrating summer circuit of FIG. 5, according to an embodimentof the invention.

FIG. 7 shows example waveforms that illustrate an operating mode of aquarter-rate feed-forward equalizer circuit that employs a 5-tapcurrent-integrating summer circuit, according to an embodiment of theinvention.

FIG. 8 is a block diagram of a 1/n-rate m-tap FFE receiver circuitaccording to an embodiment of the invention.

FIG. 9 is a schematic circuit diagram of a current-integrating amplifiercircuit according to another embodiment of the invention, which can beused to implement the n-tap current-integrating summer circuit shown inFIG. 3.

FIG. 10 is a schematic circuit diagram of a current-integrating summercircuit which implements n feed-forward taps and m decision feedbacktaps, according to another embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a feed-forward equalizer architecture forwhich embodiments of the invention can be implemented. In particular,FIG. 1 illustrates a receive-side n-tap feed-forward equalizer circuit100 comprising delay circuitry 110, multiplication circuitry 120comprising a plurality of analog multipliers (M0, M1, . . . , Mn−1), andsummer circuitry 130. The delay circuitry 110 comprises a plurality ofdelay cells (D1, D2, . . . , Dn−1). An input signal X0 is input to thedelay circuitry 110, wherein the delay cells (D1, D2, . . . , Dn−1)generate respective delayed versions(X1, X2, . . . , Xn−1) of the inputsignal X0. The signals (X0, X1, X2, . . . , Xn−1) are input torespective analog multipliers (M0, M1, M2, . . . , Mn−1), where they aremultiplied (weighted) with respective FFE weighting coefficients (C0,C1, C2, . . . , Cn−1). The outputs of the analog multipliers (M0, M1,M2, . . . , Mn−1) are summed in the summer circuitry 130 to generate anequalized signal Y1. In the embodiment of FIG. 1, the delayed signal X1may be deemed a main-cursor, where the input signal X0 is a pre-cursor,and the delayed signals (X2, Xn−1) are post-cursors. Challenges inimplementing an FFE circuit as shown in FIG. 1 include (a) generatingtime-shifted versions of the input analog signal, (b) performingcoefficient multiplication and (c) summing up the weighted signals. Asdiscussed in further detail below, exemplary embodiments of theinvention include circuits and methods to address challenges (a) and (c)above.

The delay circuitry 110 can be implemented using analog delay circuitrythat makes multiple time-delayed versions of the input data signalavailable simultaneously. Conceptually, the delay lines are analog shiftregisters that delay the incident data signal by a precise amountwithout introducing any distortions to the analog signal. The delaylines may be active or passive delay cells. In multi-gigabit/s wire linetransceiver applications, where area and power efficiency are importantconsiderations, these delay cells are undesirable for various reasons.

For instance, at high data-rates, the bandwidth of the delay cellsshould be greater than the signal bandwidth so that the delay cells donot distort the input signal. This requires active delay cells to havehigh current consumption, which is power-inefficient. Alternatively, ifinductors are used to extend the bandwidth of the active delay cells,the area footprint of the delay cells is increased. Passive delay cellsalso require area-intensive components like inductors and capacitors.Furthermore, it is difficult to tune the amount of delay of the delaycells, limiting their use in transceivers that need to operate at a widerange of data-rates to comply with different networking standards.

One way to implement the delay circuitry 110 of FIG. 1 is to use a bankof sample-and-hold (S/H) circuits which are clocked by multiphaseclocks, to thereby generate multiple time-shifted versions of an inputsignal. For example, FIG. 2A is a block diagram of a feed-forwardequalizer circuit comprising a bank of sample-and-hold circuits togenerate time-shifted data signals. In particular, FIG. 2A illustrates aquarter-rate feed-forward equalizer circuit 200 comprising delaycircuitry 210 and multiplication and summer circuitry 220. The delaycircuitry 210 comprises four parallel sample-and-hold circuits 211, 212,213 and 214, which sample an input data signal. A first sample-and-holdcircuit 211 comprises a first switch S11 and a first capacitor C11. Asecond sample-and-hold circuit 212 comprises a second switch S12 and asecond capacitor C12. A third sample-and-hold circuit 213 comprises athird switch S13 and a third capacitor C13. A fourth sample-and-holdcircuit 214 comprises a fourth switch S14 and a fourth capacitor C14.The switches S11, S12, S13 and S14 of the respective sample-and-holdcircuits 211, 212, 213 and 214 are switchably controlled by respectiveclock signals CLK0, CLK90, CLK180 and CLK270, which have distinct phases(i.e., 90 degrees phase shift) from each other.

An incoming data signal is input to each of the sample-and-hold circuits211, 212, 213 and 214 and sampled at different times in response toactivation of the respective switches S11, S12, S13, and S14 by the 90degree phase-shifted signals CLK0, CLK90, CLK180, and CLK270,respectively. The signals X0, X1, X2, and X3 output from thesample-and-hold circuitry 210 represent time-delayed versions of theincoming data signal. The signals X0, X1, X2 and X3 output from thesample-and-hold circuitry 210 are input to the multiplication and summercircuitry 220, where the signals are multiplied by correspondingcoefficients and summed to obtain FFE data outputs data0, data1, data2,and data3.

FIG. 2B shows example waveforms that illustrate an operating mode of thefeed-forward equalizer circuit shown in FIG. 2A. In the exemplaryquarter-rate receiver architecture, four phase-shifted quadrature clocksignals CLK0, CLK90, CLK180 and CLK270 having 25% duty-cycle are shown,which control the sample-and-hold circuits 211, 212, 213 and 214,respectively. When the clock signals CLK0, CLK90, CLK180 and CLK270 arelogic “high”, the respective sample-and-hold circuits 211, 212, 213 and214 will track their respective data signals, and their outputs aredeemed invalid during this time of acquisition. Thus, each data signalX0, X1, X2, and X3 is held constant for three unit intervals (UIs) andis invalid in the fourth UI.

Although FIGS. 2A and 2B illustrate a quarter-rate receiver, theseconcepts equally apply for rates other than ¼. More generally, in a1/n-rate receiver, there are n parallel sample-and-hold circuits and, ifthe clocks are high for one UI, each of the output data signals is heldconstant for (n−1) UI and invalid for one UI. Thus, at any given timeinstant, only (n−1) data samples are available for the FFE computation,implying that the FFE can have at most (n−1) taps. For example, as shownin FIG. 2B, a summing interval is one UI, and includes at most threedata samples (e.g., X1, X2 and X3). Thus, for a quarter-rate receiver,only a 3-tap FFE may be implemented using a multi-phase sample-and-holdapproach as shown in FIG. 2A.

Embodiments of the invention include FFE architectures that employcurrent-integrating summer circuitry as part of the multiplication andsummer circuits (e.g., block 220 of FIG. 2A) to overcome the above-notedlimitation on the number of taps in the equalizer when sample-and-holdcircuits (e.g., block 210, FIG. 2A) are employed to generate thetime-shifted input signals. As explained in further detail below,increasing a number of taps beyond the (n−1) limitation as noted aboveis achieved by using current-integrating summer circuitry and extendinga summing interval (or integration interval) beyond 1 UI, whereby theFFE taps whose input data-signals are not available for the entireduration of the integration are enabled only when their inputs are beingheld by the S/H circuits. The current-integrating summer circuitrystores the contributions of the FFE taps for the remainder of theintegration interval so that the proper FFE-equalized voltage can besampled at the end of the integration period.

For example, FIG. 3 is a block diagram of a current-integrating summercircuit according to an embodiment of the invention. In particular, FIG.3 illustrates an embodiment of a current-integrating summer circuit 300that can be implemented in a feed-forward equalizer circuit to achievean extended tap range. The current-integrating summer circuit 300comprises a plurality of transconductance cells 302 (or G_(m)-cells)whose output nodes are commonly connected to first and seconddifferential output nodes OUT and OUTB. The transconductance cells 302shown in FIG. 3 comprise a plurality (n) of G_(m)-cells (G_(m)-cell₀,G_(m)-cell₁, . . . , G_(m)-cell_(n−1)) for implementing an n-tapfeed-forward equalizer, as will be explained in further detail below.The current-integrating summer circuit 300 further comprises first andsecond switches S1 and S2, first and second capacitors C₁ and C₂, and atiming signal generator circuit 304. The first and second switches S1and S2 are connected between a first power supply node P1 and the firstand second differential output nodes OUT and OUTB, respectively. Thefirst and second capacitors C₁ and C₂ are connected between a secondpower supply node P2 and the first and second differential output nodesOUT and OUTB, respectively. In one embodiment of the invention, thefirst and second power supply nodes P1 and P2 may be connected to thesame power supply voltage (e.g., VDD). In another embodiment, the firstand second power supply nodes P1 and P2 may be connected to differentpower supply voltages. In another embodiment, one of the first andsecond power supply nodes P1 and P2 may be grounded and the other oneconnected to a power supply voltage.

The timing signal generator circuit 304 generates a reset control signalto switchably control the first and second switches S1 and S2. Inaddition, the timing signal generator circuit 304 generates a pluralityof gating control signals, gate₀, gate₁, . . . , gate_(n−1), which areinput to respective transconductance cells G_(m)-cell₀, G_(m)-cell₁, . .. , G_(m)-cell_(n−1), to enable or disable the respectivetransconductance cells depending on the polarity of the gating controlsignals. When the first and second switches S1 and S2 are closed(activated) in response to the reset control signal, the first andsecond capacitors C1l and C2 are connected to the first power supplynode P1 and precharged to a voltage V_(precharge). When switches S1 andS2 are opened (deactivated) in response to the reset signal, the firstand second capacitors C₁ and C₂ integrate the output currents (I_(out))from each of the transconductance cells 302 to develop a differentialvoltage at the first and second differential output nodes OUT and OUTB.

FIG. 4A is a schematic circuit diagram of a current-integratingamplifier circuit according to an embodiment of the invention, which canbe used to implement the n-tap current-integrating summer circuit shownin FIG. 3. In particular, FIG. 4A shows a current-integrating amplifiercircuit 400 comprising a transconductance cell 402 (more generally,G_(m)-cell_(k)), first and second PMOS transistors MP1 and MP2, andfirst and second capacitors C₁ and C₂. The first and second PMOStransistors MP1 and MP2 are connected between a first power supply nodeP1 and first and second differential output nodes OUT and OUTB,respectively. The PMOS transistors MP1 and MP2 are embodiments of thefirst and second switches S1 and S2 shown in FIG. 3. The first andsecond capacitors C1 and C2 are connected between the first and seconddifferential output nodes, respectively, and a second power supply nodeP2 (e.g., ground).

As further depicted in FIG. 4A, the transconductance cell 402 comprisesa differential input stage comprising a differential input pair of NMOStransistors MN1 and MN2, a source degeneration resistor Rk, NMOSswitches MN3 and MN4, and NMOS tail transistors MN5 and MN6. Thedifferential input pair of transistors MN1 and MN2 have gate terminalsthat receive differential input signals Ck·Xk and Ck·Xk, respectively,wherein Xk denotes a data input for the given transconductance cell 402and Ck is the weight value applied to the data input Xk for the giventransconductance cell 402. The differential input pair of transistorsMN1 and MN2 have drain terminals that are connected to the first andsecond differential output nodes OUT and OUTB, respectively. The firstand second capacitors C₁ and C₂ serve as resettable load capacitors forthe differential input pair of transistors MN1 and MN2. For highestpower efficiency, the first and second capacitors C₁ and C₂ may berealized as parasitic capacitances of associated wiring and devices.

Moreover, the NMOS transistors MN3 and MN4 have commonly connected gateterminals that receive a gating control signal, gatek which serves toenable or disable the transconductance cell 402. The tail transistorsMN5 and MN6 are NMOS transistors that serve as tail current sources togenerate a bias current I_(biask) to bias the differential input stage,based on a bias voltage V_(biask) that is commonly applied to the gateterminals of transistors MN5 and MN6. The degeneration resistor Rk andtwo separate tail current sources MN5 and MN6 provide resistive sourcedegeneration, which improves the linearity of the transconductance cell402.

FIG. 4B shows example waveforms that illustrate an operating mode of thecurrent-integrating amplifier circuit 400 of FIG. 4A, according to anembodiment of the invention. FIG. 4B illustrates a reset control signalthat is applied to the gate terminals of the PMOS transistors MP1 andMP2. The reset control signal is a clock waveform, alternating betweenhigh and low voltage levels, which sets a “reset period” and an“integration period” of the current-integrating amplifier circuit 400.FIG. 4B further illustrates output voltage waveforms that are generatedon the first and second differential output nodes OUT and OUTB. AlthoughFIG. 4B does not specifically show a gating control signal gatek, it isassumed in FIG. 4B that the gating control signal is asserted such thatthe transconductance cell 402 is enabled at all times , or at leastenabled during the integration period shown in FIG. 4B. In operation,when the reset control signal is logic low, the current-integratingamplifier circuit 400 is in reset mode for a given “reset period.”During the reset period, the PMOS transistors MP1 and MP2 are activated(turned on) in response to a logic low level of the reset control signalapplied to the gate terminals thereof. With PMOS transistors MP1 and MP2activated, the first and second differential output nodes OUT and OUTBare pulled up to the first power supply node P1 and precharged to avoltage level Vprecharge (e.g., approximately VDD).

As further shown in FIG. 4B, when the reset control signal transitionsto logic high, the current-integrating amplifier circuit 400 enters anintegration mode for a given “integration period.” During theintegration period, the PMOS transistors MP1 and MP2 are deactivated(turned off) in response to a logic high level of the reset controlsignal applied to the gate terminals thereof With PMOS transistors MP1and MP2 deactivated, the drain currents of the differential input pairof NMOS transistors MN1 and MN2 (which are driven by respective inputsCk·Xk and Ck·Xk) begin to discharge the first and second load capacitorsC₁ and C₂. During the “integration” period, charge is integrated(negatively) on the first and second capacitors C₁ and C₂, therebygenerating a differential voltage on the output nodes OUT and OUTBproportional to the input signal and the gain of the stage. With anonzero differential input voltage, the drain currents from thedifferential input pair of NMOS transistors MN1 and MN2 are unequal, sothe output nodes OUT and OUTB are discharged at different rates. Apositive or negative differential output voltage is developed by the endof the integration period, as indicated by the voltage waveforms of thedifferential output nodes OUT and OUTB, as shown in FIG. 4B. When thereset control signal transitions to logic low again, the PMOS switchesMP1 and MP2 are again turned on, and the differential output nodes OUTand OUTB are pulled up to the first power supply node P1 and prechargedto a voltage level Vprecharge (e.g., approximately VDD).

FIG. 5 is a schematic circuit diagram of a 4-tap current-integratingsummer circuit for a feed-forward equalizer circuit, which is based onthe circuit structures of FIGS. 3 and 4A, according to an embodiment ofthe invention. In particular, FIG. 5 illustrates a 4-tapcurrent-integrating summer circuit 500 which is based on the frameworkshown in FIG. 3, wherein the 4-tap current-integrating summer circuit500 comprises a plurality of transconductance cells 502 which includesfour G_(m)-cells (G_(m)-cell₀, G_(m)-cell₁, . . . , G_(m)-cell₃). Eachof the transconductance cells (G_(m)-cell₀, G_(m)-cell₁, . . . ,G_(m)-cell₃) has topology that is based on the transconductance cell 402shown in FIG. 4A. For clarity, the third transconductance cell (i.e.,G_(m)-cell₂) is not shown in FIG. 5, and it is assumed that thetransconductance cell G_(m)-cell₂ represents the main cursor of the4-tap architecture.

As shown in FIG. 5, each transconductance cell 502 comprises adifferential input stage including a differential input pair of NMOStransistors MN1 and MN2 which receive differential input signals (C0·X0/C0·X0 ), (C1·X1/ C1·X1 ), (C2·X2/ C2·X2 ), and (C3·X3/ C3·X3 ),respectively, wherein X0, X1, X2 and X3 denote the data inputs for therespective transconductance cells 502 and C0, C1, C2 and C3 denote arespective weight value applied to the respective data inputs X0, X1, X2and X3. Furthermore, each transconductance cell 502 comprises arespective source degeneration resistor R0, R1, R2 and R3. Moreover,each transconductance cell 502 comprises NMOS transistors MN3 and MN4that receive respective gating control signals gate₀, gate₁, gate₂, andgate₃, which serve to enable or disable the respective transconductancecell 502. Furthermore, each transconductance cell 502 comprises tailtransistors MN5 and MN6 that serve as tail current sources to generaterespective bias currents I_(bias0), I_(bias1), I_(bias2), and I_(bias3)based on respective bias voltages V_(bias0), V_(bias1), V_(bias2),V_(bias3).

In the structure shown in FIG. 5, the drain terminals of each linearsource-degenerated transconductance stage 502, whose input voltagesrepresent the product of the data signals and coefficients, are dottedtogether so that the currents proportional to each term in the FFEcomputation are summed up at the output nodes OUT and OUTB. In someembodiments, the input voltages to the transconductance stages 502 arethe data signals X0, X1, X2, X3, wherein coefficient multiplication isimplemented by varying the value of the source degeneration resistorsR0, R1, R2, and R3 to change the effective transconductance of each ofthe stages. In other embodiments, different multiplication factors canbe achieved by changing the size (ratio) of the differential inputtransistors MN1/MN2 to achieve different Gm values for each stage, or byvarying the bias voltages to obtain different bias currents for thedifferent stages, etc. In all embodiments, since the output terminals ofeach of the transconductance cells 502 are commonly connected to thedifferential output nodes OUT and OUTB, the currents from the differenttransconductance cells 502 are summed by “dotting”, and the dischargerate of the differential output nodes during an integration intervalrepresents the mathematical addition of the multiple input signals(weighted by the transconductances of the respective input stages).

FIG. 6 shows example waveforms that illustrate an operating mode of aquarter-rate feed-forward equalizer circuit that employs the 4-tapcurrent-integrating summer circuit of FIG. 5, according to an embodimentof the invention. FIG. 6 shows four phase-shifted quadrature clocksignals CLKO, CLK90, CLK180 and CLK270 having a 25% duty-cycle for aquarter-rate receiver architecture. For purposes of illustration, it isassumed that the four phase-shifted quadrature clock signals CLK0,CLK90, CLK180 and CLK270 control respective sample-and-hold circuits211, 212, 213 and 214, of the sample and hold circuitry 210 shown inFIG. 2A. FIG. 6 further shows 4 data sample waveforms X0, X1, X2 and X3that are generated using the sample and hold circuitry 210 of FIG. 2A inresponse to the four quadrature clock signals CLK0, CLK90, CLK180 andCLK270. FIG. 6 further shows a plurality of control signals including areset signal and a plurality of gating signals gate₀, gate₁, and gate₃In the embodiments of FIGS. 5 and 6, it is assumed that thetranconductance cell G_(m)-cell₂ (not specifically shown in FIG. 5) andcorresponding data input X2 represent the main cursor FFE tap, the datainput X0 is a second post-cursor, the data input X1 is a firstpost-cursor, and that the data input X3 is a pre-cursor.

In the framework of FIG. 5, a 4-tap FFE is implemented by extending an“integration period” to 2 UI_, UI_1 and UI_2, and then using gatingsignals, gate_(o), gate₁ and gate₃, to ensure that the properFFE-equalized voltage is produced by the 4-tap current-integratingsummer circuit of FIG. 5. In particular, as shown in FIG. 6, the resetcontrol signal has a 50% duty cycle to provide an “integration period”of two UIs, a first UI_1 and a second UI_2. With an “integration period”of two UIs, there exists some period of time in which each data signal(X0, X1, X2 or X3) is active and valid so that a 4-tap FFE can beimplemented. This is to be contrasted with the operating mode shown inFIG. 2B where an integration period (or summing interval) of one UIallows only three data inputs (X1, X2 and X3) to contribute to the FFEcomputation.

Moreover, while certain data inputs (e.g., X0 and X3) are both valid andinvalid at certain points of time during the integration period, thegating control signals operate to disable the respectivetransconductance cells at times when the data inputs are not valid. Forinstance, as shown in FIG. 6, since the data signal X0 is invalid duringthe second unit interval UI_2 of the integration period, the gatingcontrol signal gate₀ is only asserted during the first unit intervalUI_1 of the integration period, and de-asserted during the second unitinterval UI_2 of the integration period. As such, the transconductancecell G_(m)-cell₀ of FIG. 5 is disabled during the second unit intervalUI_2 of the integration period in response to logic low gating controlsignal gate₀, so that the invalid data X0 does not contribute to the FFEcomputation. In addition, as further shown in FIG. 6, since the datasignal X3 is invalid during the first unit interval UI_1 of theintegration period, the gating control signal gate₃ is only assertedduring the second unit interval UI_2 of the integration period, andde-asserted during the first unit interval UI_1 of the integrationperiod. As such, the transconductance cell G_(m)-cell₃ of FIG. 5 isdisabled during the first unit interval UI_1 of the integration period,so that the invalid data X3 does not contribute to the FFE computation.In this manner, the gating control signals serve to disable thetransconductance cells from outputting current during periods in whichtheir respective data inputs are not valid, thereby preventing the finalFFE-equalized voltage from being corrupted by invalid data-input signalsduring the integration period.

On the other hand, for FFE taps that are available for the entireduration of integration period, such as the first post-cursor X1 andmain-cursor X2 as shown in FIG. 6, the use of gating control signals isoptional, or gating control signals can be used for other purposes. Forexample, in one embodiment of the invention, the gating control logicand gating circuit (e.g., gating transistors MN3 and MN4 of FIG. 5) maybe omitted altogether for those taps in which the input data is alwaysvalid during the integration period. For example, as shown in FIG. 6,the data inputs X1 and X2 are valid during both the first and secondunit intervals UI_1 and UI_2 of the integration period. As such, nogating control signal (e.g., gate₁ or gate₂) need be applied toenable/disable the tranconductance cell G_(m)-cell₁ or G_(m)-cell₂during the integration period.

In another embodiment, for a given FFE tap that is valid for the entireintegration period, the gating control signal may operate to turn on thegiven FFE tap for a fraction of the integration period so as to limitthe contribution of the given tap to the final FFE-equalized voltage.For instance, as shown in FIG. 6, while the first post-cursor data inputX1 is valid during both the first and second unit intervals and UI_2 ofthe integration period, the gating control signal gate₁ is shown asbeing asserted only during the second unit interval UI_2 of theintegration period. In other embodiments, the gating control signal mayturn on the FFE taps during the first unit interval UI_1 of theintegration interval or during the second half of the integrationinterval. The use of the gating control signal to limit the contributionof a given FFE tap during the integration period is one method that canbe implemented to apply a “weight” value to the corresponding datainput, i.e., the contributions of the data inputs to the finalFFE-equalized voltage are weighted based on the amount of time that thedata inputs of the FFE taps are applied during the integration period.

Furthermore, while FIG. 6 shows that the gating control signals arede-asserted (turned off) during the reset phase of thecurrent-integrating summer circuitry 500 of FIG. 5, in anotherembodiment of the invention, the gating control signals may be assertedfor some portion of the reset period as well. This serves to improvecircuit performance in high-speed applications where generation of shortpulses is difficult.

In the embodiments of FIGS. 5 and 6, each transconductance cell 502(G_(m)-cell₀, G_(m)-cell₁, . . . , G_(m)-cell₃) converts the respectivedifferential input voltage (C0·X0/ C0·X0 ), (C1·X1/ C1·X1 ), . . .(C3·X3/ C3·X3 ) to an output current during the integration period whenthe respective gating control signal gate₀, gate₁, . . . gate₃ is logichigh. Even if a gating control signal for a given transconductance cellG_(m)-cell_(k) transitions to logic low before the end of theintegration period, the contribution of the given transconductance cell,G_(m)-cell_(k), to the output voltage at the differential output nodesOUT and OUTB is held by the capacitors C₁ and C₂ until the end of theintegration period. This enables the implementation of FFEs with longerspans, since data signals that are not available for the entire durationof the integration period can now be used in the FFE computation. Due toits inherent memory, a current-integrating summer circuit such as shownin FIG. 5 stores the contribution of each of the FFE taps until thereset period, so that a proper FFE-equalized voltage can be sampled atthe end of the integration period. This makes it possible to addpre-cursors and/or post-cursors that are not valid at the same timeduring the integration period.

FIG. 7 shows example waveforms that illustrate an operating mode of aquarter-rate feed-forward equalizer circuit that implements a 5-tapcurrent-integrating summer circuit, according to an embodiment of theinvention. To implement a 5-tap current-integrating summer circuit, thecurrent-integrating circuit 500 of FIG. 5 can be modified to include anadditional transconductance cell (e.g., G_(m)-cell₄), which receives asinput a differential input voltage (C4·X0/ C4·X0 ), that includes thesame data input X0 input to the first transconductance cell G_(m)-cell₀,but with a different weight C4.

Moreover, as shown in FIG. 7, an integration interval is extended toinclude three unit intervals UI_1, UI_2 and UI_3, with a reset signalhaving a 75% duty cycle, and gating control signals gate₀, gate₁, gate₃,and gate₄ are used to control respective transconductance cells,G_(m)-cell₀, G_(m)-cell₁, G_(m)-cell₃, and G_(m)-cell₀ toensure that aproper FFE-equalized voltage is produced at the differential outputnodes OUT/OUTB of the current-integrating summer at the end of theintegration period. As shown in FIG. 7, each gating signal is assertedonly when the corresponding data signal is valid. As further shown inFIG. 7, the second post-cursor and second pre-cursor are derived fromthe same signal, X0, but weighted with different FFE coefficients (C0and C4), and controlled with different gating signals gate₀ and gate₄,respectively.

FIG. 8 is a block diagram of a 1/n-rate, m-tap FFE receiver circuitaccording to an embodiment of the invention. In particular, FIG. 8illustrates a FFE receiver circuit 600 comprising a clock generator 605,sample-and-hold circuitry 610, buffer circuitry 615, and a plurality ofn parallel receiver slices (620_0, . . . , 620_n−1). In one embodiment,the sample-and-hold circuitry 610 comprises n parallel sample-and-holdcircuits, such as shown in FIG. 2A (e.g., n=4) to implement a (1/n)-rateFFE receiver. Each of the n receiver slices (620_0, . . . , 620_n−1)comprises an m-tap current-integrating summer circuit 602, a timingsignal generator circuit 604, and a latch 622. In one embodiment, thecurrent-integrating summer circuits 602 and timing signal generatorcircuits 604 in each of the n receiver slices (620_0, . . . , 620_n−1)are implemented using the circuit structure of FIG. 3, for example.

The clock generator 605 receives an input CLOCK and generates a firstset of n phase-shifted clock signals (CLK₀, . . . , CLK_(n−1)) thatclock respective ones of the n parallel sample-and-hold circuits of thesample-and-hold circuitry 610. The first set of n phase-shifted clocksignals (CLK₀, . . . , CLK_(n−1)) have duty-cycles that may or may notbe 50%. In one embodiment, the first set of n phase-shifted clocksignals (CLK₀, . . . , CLK_(n−1)) include n=4 phase-shifted quadratureclock signals CLK0, CLK90, CLK180 and CLK270 having a 25% duty-cycle, asin the example embodiments discussed above. The clock generator 605further generates a second set of n phase-shifted clocks (CK₀, . . . ,CK_(n-1)) that are distributed to the timing signal generator circuits604 in each of the n receiver slices (620_0, . . . , 620_n−1). In oneembodiment of the invention, the second set of n phase-shifted clocksignals (CK₀, . . . , CK _(n−1)) have rising edges that are aligned tothe rising edges of corresponding ones of the first set of nphase-shifted clock signals (CLK₀, . . . , CLK _(n−1)), and haveduty-cycles that match or do not match the first set of n phase-shiftedclock signals (CLK₀, . . . , CLK_(n−1)). Each timing signal generatorcircuit 604 comprises Boolean combinatorial logic circuitry to process asubset of the clocks (CK₀, . . . , CK_(n−1)) to produce gating controlsignals gate₀, . . . , gate_(m−1) and reset signals for thecurrent-integrating summer circuits 602 in each of the n receiver slices(620_0, . . . , 620_n−1).

The sample-and-hold circuitry 610 receives an input data stream having abit rate of Y bits/sec, and generates n output streams X0, . . . , Xn−1which are distributed in parallel to each of the current-integratingsummer circuits 602 in each of the n receiver slices (620_0, . . . ,620_n−1). For example, assuming that n=4 and the bit rate of the inputdata signal is 20 Gb/s, the sample-and-hold circuitry 610 outputs n=4streams of data, X0, X1, X2 and X3 each having a sampling rate of 5Gsamples/s. In one embodiment, the outputs of the sample-and-holdcircuitry are input to respective buffers B₀, . . . , B_(n−1) of thebuffer circuitry 615, where the output data streams X0, X1, X2 . . . ,Xn−1 can be buffered to improve the bandwidth of the sample-and-holdcircuitry 610.

In the embodiment of FIG. 8, the current-integrating summer circuits 602in each of the n receiver slices (620_0, . . . , 620_n−1) can beimplemented using any one of the embodiments discussed herein, such asin FIGS. 5, 6, and 7, wherein each current-integrating summer circuit602 comprises m transconductance cells (FFE taps). Depending on theapplication, each timing signal generator circuit 604 generates at mostm gating control signals (or less in some embodiments where one or moretransconductance cells are not gated). The outputs out₀, . . . ,out_(n−1) of the respective current-integrating summer circuits 602 areinput to respective decision-making latch circuits 622, each of whichoutputs a respective one of the n data streams, data₀, . . . ,data_(n−1), based on the FFE computation. In the embodiment of FIG. 8,the number of current-integrating FFE taps m can be greater than orequal to n, or m can be less than n.

FIG. 9 is a schematic circuit diagram of a current-integrating amplifiercircuit according to another embodiment of the invention, which can beused to implement the n-tap current-integrating summer circuit shown inFIG. 3. More specifically, FIG. 9 illustrates a current-integratingamplifier circuit 700 which is similar to the current-integratingamplifier circuit 400 of FIG. 4A, but which further includes additionaltransistors MN7 and MN8 to steer the currents in the given FFE tap to areference node when the gating control signal (gate_(k)) turns off theFFE tap. More specifically, as shown in FIG. 9, the NMOS transistor MN7is connected between the first power supply node P1 and a drain terminalof the tail current source transistor MN5, and the NMOS transistor MN8is connected between the first power supply node P1 and a drain terminalof the tail current source transistor MN6. A complementary gatingcontrol signal gate_(k) is applied to the gate terminals of the NMOStransistors MN7 and MN8. As such, when the given FFE tap is disabled bya logic low gating control signal, i.e., gate_(k)=logic low, then theNMOS transistors MN7 and MN8 are turned on in response to thecomplementary (logic high) signal gate_(k) , which keeps the currentsource transistors MN5 and MN6 in saturation even when the FFE tap isturned off. This circuit structure improves the accuracy of the FFEcomputation by avoiding unwanted surge currents that would otherwiseintroduce errors caused by repeatedly turning on and off the currents inthe tail transistors MN5 and MN6 when the gating control signal gate_(k)enables and disables the FFE tap.

While the embodiments described thus far employ gating transistors MN3and MN4 that are responsive to a gating control signal gate_(k) toenable and disable the FFE taps, the gating operation can be implementedusing other techniques. For example, in one embodiment of the invention,a gating operation is implemented by switchably coupling the gateterminals of the tail current source transistors MN5 and MN6 to groundvoltage to disable the FFE tap. In another embodiment, the gateterminals of the FFE input differential transistor pair MN1 and MN2 maybe disconnected from the FFE input signals and connected to acommon-mode signal to disable the FFE tap. In yet another embodiment,the gating transistors MN3 and MN4 of each FFE tap are connected betweenthe differential input transistor pair MN1 and MN2 and thesource-degenerating resistor Rk.

In other embodiments of the invention, a current-integrating summercircuit can be implemented using both FFE taps and DFE (decisionfeedback equalization) taps. For example, FIG. 10 is a schematic circuitdiagram of a current-integrating summer circuit which implements nfeed-forward taps and m decision feedback taps, according to anotherembodiment of the invention. More specifically, FIG. 10 illustrates acurrent-integrating summer circuit 700 which comprises a plurality of nFFE taps 702 and a plurality of m DFE taps 704. The FFE taps 702comprise a main cursor stage and (n−1) FFE pre-cursor and post-cursortaps. The n FFE taps 702 are constructed using transconductance cellssuch as discussed above with reference to FIGS. 4A and 5, for example.In the embodiment of FIG. 10, the main cursor stage of the FFE taps 702does not include gating transistors MN3 and MN4, wherein it is assumedthat the data input X1 for the main cursor is valid during an entireintegration period.

Furthermore, as shown in FIG. 10, each of the m DFE taps comprises adifferential transistor pair MN9 and MN10 that receives as input,different feedback taps, generally denoted H_(k) and H_(k) . In general,as is well-understood by those of ordinary skill in the art, a DFE usesthe history of previously decided bits to calculate their contributionsto the intersymbol interference (ISI) of the current bit so that the ISIcan be cancelled. More specifically, in a DFE, the previously decidedbits are fed back with weighted tap coefficients and added to thereceived input signal. For an m-tap DFE, the feedback taps are H1, H2, .. . , Hm. The H1 tap represents the ISI contributed by a data bit one UIearlier than the current bit being detected, the H2 tap represents theISI contributed by a data bit two UIs earlier than the current bit, andso on. If the magnitudes and polarities of the tap weights are properlyadjusted to match the channel characteristics, the ISI from the previousbits in the data stream will be cancelled, and the bits can be detectedby a decision-making latch with a low BER (bit error rate).

Other straightforward modifications and variations of the disclosedembodiments, such as changing NMOS transistors to PMOS types, and viceversa, will be obvious to those skilled in the art. Such modificationsand variations do not depart from the spirit and scope of the invention.

Further aspects of the present invention provide FFE architectures withcurrent-integrating summer circuits as described herein, which can beutilized in integrated circuit chips with various analog and digitalintegrated circuitries. In particular, integrated circuit dies can befabricated having current-integrating summer circuits with FFE and DFEtaps and other semiconductor devices such as field-effect transistors,bipolar transistors, metal-oxide-semiconductor transistors, diodes,resistors, capacitors, inductors, etc., forming analog and/or digitalcircuits. The current-integrating summer circuits can be formed upon orwithin a semiconductor substrate, the die also comprising the substrate.An integrated circuit in accordance with the present invention can beemployed in applications, hardware, and/or electronic systems. Suitablehardware and systems for implementing the invention may include, but arenot limited to, personal computers, communication networks, electroniccommerce systems, portable communications devices (e.g., cell phones),solid-state media storage devices, functional circuitry, etc. Systemsand hardware incorporating such integrated circuits are considered partof this invention. Given the teachings of the invention provided herein,one of ordinary skill in the art will be able to contemplate otherimplementations and applications of the techniques of the invention.

Although exemplary embodiments of the present invention have beendescribed herein with reference to the accompanying figures, it is to beunderstood that the invention is not limited to those preciseembodiments, and that various other changes and modifications may bemade therein by one skilled in the art without departing from the scopeof the appended claims.

What is claimed is:
 1. A method for equalizing a data signal,comprising: generating n time-delayed versions of an input data signal;inputting m data signals to m feed-forward equalization (FFE) taps of acurrent-integrating summer circuit, wherein each of the m data signalscorresponds to one of the n time-delayed versions of the input datasignal; charging a capacitance to a precharge level during a resetperiod of the current-integrating summer circuit; generating an outputcurrent by each of the m FFE taps during an integration period of thecurrent-integrating summer circuit, wherein the output currents from them FFE taps collectively charge or discharge the capacitance during theintegration period; and applying a gating control signal to at least oneFFE tap of the m FFE taps during the integration period of thecurrent-integrating summer circuit to disable the at least one FFE tapduring a portion of the integration period in which the data signalinput to the at least one FFE tap is invalid.
 2. The method of claim 1,wherein each of the m FFE taps is a transconductance amplifier circuit.3. The method of claim 1, wherein the integration period is two or moreunit intervals in time.
 4. The method of claim 1, wherein at least twodifferent FFE taps receive as input a same data signal that correspondsto one of the n time-delayed versions of the input data signal, andwherein the at least two different FFE taps are gated by differentgating control signals.
 5. The method of claim 1, wherein at least twodifferent FFE taps receive as input different data signals thatcorrespond to different ones of the n time-delayed versions of the inputdata signal, and wherein the different data signals are not valid at asame time during the integration period.